Coming Thursday, June 27th, at 10:00 AM ET, I’ll give a webinar on “Cryogenic CMOS Interfaces for Large-Scale Quantum Computers”. The webinar is organized by the IEEE Solid-State Circuit Society and you can register to attend here.
There will be the opportunity to ask questions. I hope many of you will join!
My article in the “News and views” section of Nature Electronics has just been published on-line. You can find it freely available here: https://rdcu.be/bG4sI.
In this piece, titled “Scalable read-out schemes for qubits“, I comment on the latest results by Dr. Fernando Gonzalez-Zalba at Hitachi Cambridge Laboratory on selective DRAM-like readout of spin qubits (also published in Nature Electronics). I give my views on current state-of-the-art on electronic interfaces for solid-state quantum processors and outline the path that electrical and Quantum Engineers will have to follow to give birth to scalable quantum computers.
The work of two of my Ph.D. students has been accepted for presentation at the coming ESSCIRC/ESSDERC conferences to be held in Krakow, Poland next September. Congratulations to Job and Pascal!
Job’s work is showing how to build a voltage reference in standard CMOS that can operate over the whole ultra-wide temperature range from 4 K to 300 K. And, for the first time, we are showing significant statistical data demonstrating the accuracy of such references down to cryogenic temperature.
In the other paper by Pascal, we focus on device characterization of CMOS transistors at cryogenic temperature. We extend our prior work on cryo-CMOS mismatch by showing the characterization of transistor mismatch over a wide range of operating regimes, from strong inversion down to weak inversion. In particular, weak inversion operation is very relevant as it allows for low-power operation, as required in several power-limited cryogenic applications, such as quantum computing.
Both papers will be presented on the first day of the conference, on Tuesday morning and afternoon. See here.
References:
